Question 4 20 points (Sequential Logic flip-flops and timing diagrama) Consider the circuit illustrated in Figure 2 consisting of two positive edge-triggered D-type flip flops with selective load capability, an input bus, an output bus and two tri-state buffers in_bus clock id_koith MICK Qmick keith outbus Figure 2: A simple bus circuit Complete the timing diagram which is included at the end of this exam. Write your name and ID number in the space provided and remove the last page of this exam and insert it into your answer booklets. Indicate in the provided timing diagram the behaviour of the two flop outputs (mick and _Keith) as well as the behaviour of out_bus between the indicated “start” and “end”times Use the symbol Z to denote when the bus is in the high impedance (tri-state value) state. In the provided timing diagram, it is assumed that the initial value of _mick is logic ‘O’ and that the initial value of _Keith is logic ‘l’Note also that the timing diagram intentionally contains a fatal design error. You are to explain in words in your answer booklet) the nature of this design error and to indicate (on the provided timing diagram) when this error occurs. HINT. use the word “FIRE” to indicate the state of the out_bus at that point in time when the design error оссur. TIMONG DIAGRAM FOR QUESTION 4 hhhhh clock In_bus- Id_mick id_kwith on_mick an_Keith mick out us Show transcribed image text Question 4 20 points (Sequential Logic flip-flops and timing diagrama) Consider the circuit illustrated in Figure 2 consisting of two positive edge-triggered D-type flip flops with selective load capability, an input bus, an output bus and two tri-state buffers in_bus clock id_koith MICK Qmick keith outbus Figure 2: A simple bus circuit Complete the timing diagram which is included at the end of this exam. Write your name and ID number in the space provided and remove the last page of this exam and insert it into your answer booklets. Indicate in the provided timing diagram the behaviour of the two flop outputs (mick and _Keith) as well as the behaviour of out_bus between the indicated “start” and “end”times Use the symbol Z to denote when the bus is in the high impedance (tri-state value) state. In the provided timing diagram, it is assumed that the initial value of _mick is logic ‘O’ and that the initial value of _Keith is logic ‘l’Note also that the timing diagram intentionally contains a fatal design error. You are to explain in words in your answer booklet) the nature of this design error and to indicate (on the provided timing diagram) when this error occurs. HINT. use the word “FIRE” to indicate the state of the out_bus at that point in time when the design error оссur.
TIMONG DIAGRAM FOR QUESTION 4 hhhhh clock In_bus- Id_mick id_kwith on_mick an_Keith mick out us
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Answer to Question 4 20 points (Sequential Logic flip-flops and timing diagrama) Consider the circuit illustrated in Figure 2 cons…