(Solved) : Question 4 Building Computer Hierarchical Memory System Consists Separate Instruction Data Q42756335 . . .

Question 4] You are building a computer with a hierarchical memory system that consists of separate instruction and data caches followed by main memory. You are using the MIPS multicycle processor running at 1 GHz. (a) Suppose the instruction cache is perfect (i.e., always hits) but the data cache has a 5% miss rate. On a data cache miss, the processor stalls for 60 ns to access main memory, then resumes normal operation. Taking cache misses into account, what is the average memory access time? (b) How many clock cycles per instruction (CPI) on average are required for load and store word instructions considering the non-ideal memory system? (c) Consider the benchmark application that has 25% loads, 10% stores, 11% branches, 2% jumps, and 52% R-type instructions. Taking the non-ideal memory system into account, what is the average CPI for this benchmark? Show transcribed image text Question 4] You are building a computer with a hierarchical memory system that consists of separate instruction and data caches followed by main memory. You are using the MIPS multicycle processor running at 1 GHz. (a) Suppose the instruction cache is perfect (i.e., always hits) but the data cache has a 5% miss rate. On a data cache miss, the processor stalls for 60 ns to access main memory, then resumes normal operation. Taking cache misses into account, what is the average memory access time? (b) How many clock cycles per instruction (CPI) on average are required for load and store word instructions considering the non-ideal memory system? (c) Consider the benchmark application that has 25% loads, 10% stores, 11% branches, 2% jumps, and 52% R-type instructions. Taking the non-ideal memory system into account, what is the average CPI for this benchmark?

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Answer to Question 4] You are building a computer with a hierarchical memory system that consists of separate instruction and data…