reg_file
This register file provides two read ports, one write port, andone PC (R15) update port. The ports are:
module reg_file( output reg32_t rn, rm, input reg32_t rd, input reg32_t pc, input reg_sel_t n, m, d, input logic dw, reset, clk);
The reg_sel_t has to index 16 registers and is defined as
typedef logic [3:0] reg_sel_t;
The PC, R15, is updated on every positive clock edge as long asd is not equal to 15. If d is 15 and dw is 1 then the rd port willbe updated by the input rd, otherwise R15 is updated by pc. Theregister output, rn, is selected by n. The register output, rm. isselected by m. The register input, rd. is selected by d. When resetis 1, all the registers are set to zero.
Implement the reg_file module. Hint: base your design on thereg_file module in the Register Files, RAM, and ROM inVerilog notes. The main differences are the update of the PCand the registers are 32 bits.
The following works for everything except updating the pc:
module reg_file( output reg16_t rn, rm, input reg16_t rd, input reg_sel_t n, m, d, input logic dw, reset, clk); reg16_t R[7:0]; // registers integer i; // two read registers // each register is independent assign rn = R[n]; assign rm = R[m]; // one write register, write can occur in paralle always_ff @(posedge clk) begin if ( reset ) begin for( i = 0; i < $size(R); i++) begin R[i] <= 0; end end else if ( dw ) R[d] <= rd; endendmodule
Test bench:
typedef logic [31:0] reg32_t;typedef logic [3:0] reg_sel_t;module main; reg32_t rn, rm, rd; reg_sel_t n, m, d, rsel; logic dw, reset, clk; reg32_t pc_in; reg32_t data_v; integer index; logic pass_fail = 1; reg_file dut( rn, rm, rd, pc_in, n, m, d, dw, reset, clk); task automatic reset_reg; reset = 1; clk = 0; #5; clk = 1; #5; reset = 0; endtask task automatic write_rd( input reg_sel_t sel, input reg32_t data ); dw = 1; // enable write d = sel; // select target register rd = data; // set the data values clk = 0; #5; clk = 1; #5; // clock the register file dw = 0; // disable register write endtask task automatic read_rn( input reg_sel_t sel, output reg32_t data ); n = sel; // select register to read #10; data = rn; // get value endtask task automatic read_rm( input reg_sel_t sel, output reg32_t data ); m = sel; #10; data = rm; endtask task automatic check_pc( input reg_sel_t sel, input reg32_t data, pc_data ); reg32_t readback; $display(“Checking PC %8x”, pc_data); pc_in = pc_data; write_rd( sel, data); read_rn( sel, readback ); if ( data !== readback ) begin $display( “Rn = %8x, expected = %8x”, readback, data ); pass_fail = 0; end read_rn( 15, readback ); if ( pc_data !== readback ) begin $display( “PC = %8x, expected = %8x”, readback, pc_data ); pass_fail = 0; end endtask task automatic check_pc_r15( input reg32_t data, pc_data ); reg32_t readback; $display(“Checking R15 %8x”, data); pc_in = pc_data; write_rd( 15, data); read_rn( 15, readback ); if ( data !== readback ) begin $display( “PC = %8x, expected = %8x”, readback, data ); pass_fail = 0; end endtask initial begin reset_reg; // write all the registers with 0,1,2, .. 15 for( index=0; index < 1<<$bits(d); index = index + 1 ) begin write_rd( index, index+1 ); end $display(“Checking Register N”); // output values using register n for( index=0; index < 1<<$bits(n); index = index + 1 ) begin read_rn( index, data_v ); if ( data_v !== index+1 ) begin $display( “Rn[%0d] = %8x, expected = %8x”, index, data_v, index+1); pass_fail = 0; end end $display(“Checking Register M”); // output values using register m for( index=0; index < 1<<$bits(m); index = index + 1 ) begin read_rm( index, data_v ); if ( data_v !== index+1 ) begin $display( “Rm[%0d] = %8x, expected = %8x”, index, data_v, index+1); pass_fail = 0; end end check_pc( 0, 10, 20 ); check_pc( 1, 30, 24 ); check_pc( 2, 20, 34 ); check_pc_r15(30, 36 ); if ( pass_fail ) $display(“nnTest passed”); else $display(“nnTest failed”); $finish; endendmodule
I am stuck on how to update the pc so any help with how to goabout this would be appreciated.
Expert Answer
Answer to reg_file This register file provides two read ports, one write port, and one PC (R15) update port. The ports are: module…