You are required to design and implement an ALU withthe following ports:

• A and B are inputs, and are n-bit signed numbers represented in2’s complement

• F is 3-bit unsigned number for ALU function selector

• R is the signed ALU result represented in 2’s complement. Youwill have to

determine the minimum number of bits required for R such that anoverflow

never occurs.

Below is a table of ALU functions along with an illustration of itsport interface

Function Code ALU Result

F=000 R=(A+B)/2

F=001 R=2*(A+B)

F=010 R=A/2 + B

F=011 R=A – B/2

F=100 R=A nand B

F=101 R= not(A)

F=110 R=A nor B

F=111 R=A xor B

a) (5 points) Determine the size of R in bits such that overflowcan never occur.

b) (10 points) Show the implementation of the ALU using MSIcomponents and the

minimum number of additional gates. Hint: you will have to use someform of

extension (zero- or sign-extension).

c) (10 points) Create behavioral Verilog modules for every MSIcomponent you used in

Part (b). Make sure the size of every module you design isparameterized, so that you

can change your design easily during the testing phase.

d) (5 points) Create a structural model for your ALU designed inPart (b) using the

modules you derived in Part (c).

e) (5 points) Write a Verilog test bench that tests your ALU modulein Part (d) assuming

that A and B are 4-bits using the following input values:

A B F Expected output

3 3 1 R=12

2 5 0 R=3

-2 -4 1 R=-12

Allow a period of 20 ps between two consecutive test cases.

f) (5 points) Write a single behavioral Verilog module that modelsthe given ALU.

g) (5 points) Write a Verilog test bench to test your behavioralALU model in Part (f).

Assuming that A and B are 4-bit, use the following inputvalues:

A B F Expected output

3 3 1 R=12

2 5 0 R=3

-2 -4 1 R=-12

Allow a period of 20 ps between two consecutive test cases.

h) (5 points) Submit a report (Word or PDF document) that shouldcontain:

i. Problem description

ii. Your answers to Parts (a) and (b)

iii. All the behavioral models derived in Part (c), structuralmodel in Part (d), and the

test bench in Part (e)

iv. The behavioral model in Part (f) and its test bench in Part(g)

v. The timing diagrams (waveforms) taken directly as snapshots fromthe simulator.

Have as many snapshots as needed to cover all the test cases.

Q.1. You are required to design and implement an ALU with the following ports: • A and B are inputs, and are n-bil signed numbers represented in 2’s cxplement . F is 3-bit unsigned number for ALU function sclector . Ris the signe ALU result represented in 2′ plement. You will have to determine the minimum Turner l’ils ruinel lor Ruch that never low never EXCUS. Below is a table of ALU functions along with an illustration of its port interface Fun C -000 ALU Symbol ALL RS R-D2 R-TAR) R-A2-R – R-A-B2 R- AR F ALU TE011 FINS F-101 r-10 a) 15 points, Determine the size of R in bits such that overflow can never occur. b) 10 points Show the implementation of the ALU using MSI components and the minimum number of additional gatos. Hint: you will have to use some form of extension (zero- or sign-cxtcasion). c) (10 points) Create hehavioral Verilg modules for every MSI Corneni yeni in Part by. Make sure the size of every module you design is parameterized, so that you can change your design casily during the testing phase. d) 15 points) Create a structural model for your ALU designed in Pant (b) using the modules you derived in Part I). e) 15 points) Write a Verilog test bench that tests your ALL module in Partid) assuming that A and B are 4-bits using the following input valucs: AD Lxpected output 33 IR-12 25 DR- 24R-12 Allow a period of 20 ps between two consecutive test cases. 1) 5 points) Write a single behavioral Verilog module that models the givea ALU. g) 15 polots) Write a Verilog test bench to test your behavioral ALU model in Part 1f). Assuming that A and B auct-bit. use the following input values: REE R-12 SDR -2 HTR2 Alla period 20 ps here in consecutive les cases. (5 points) Subalit a report (Word or PDF document) that should contain- 2/2 h) i. Problem description il. Your answers to Parts(a) and (b) iii. All the behavioral models dcrived in Part 1, structural model in Part (di, and the test hench in Parl() iv. Thehavioral mcxlel in Pant (and its test hench in Part 1 . The timing diagrams (waves ) taken directly as snapshots rum the simulate Ilave as many ashes as needed in cover all the best caves The assignmcat can be solved individually, or in groups of two studcats. Submit a soft copy of your solution on Blackboard in a zip filc including your Verilog models. Show transcribed image text Q.1. You are required to design and implement an ALU with the following ports: • A and B are inputs, and are n-bil signed numbers represented in 2’s cxplement . F is 3-bit unsigned number for ALU function sclector . Ris the signe ALU result represented in 2′ plement. You will have to determine the minimum Turner l’ils ruinel lor Ruch that never low never EXCUS. Below is a table of ALU functions along with an illustration of its port interface Fun C -000 ALU Symbol ALL RS R-D2 R-TAR) R-A2-R – R-A-B2 R- AR F ALU TE011 FINS F-101 r-10 a) 15 points, Determine the size of R in bits such that overflow can never occur. b) 10 points Show the implementation of the ALU using MSI components and the minimum number of additional gatos. Hint: you will have to use some form of extension (zero- or sign-cxtcasion). c) (10 points) Create hehavioral Verilg modules for every MSI Corneni yeni in Part by. Make sure the size of every module you design is parameterized, so that you can change your design casily during the testing phase. d) 15 points) Create a structural model for your ALU designed in Pant (b) using the modules you derived in Part I). e) 15 points) Write a Verilog test bench that tests your ALL module in Partid) assuming that A and B are 4-bits using the following input valucs: AD Lxpected output 33 IR-12 25 DR- 24R-12 Allow a period of 20 ps between two consecutive test cases. 1) 5 points) Write a single behavioral Verilog module that models the givea ALU. g) 15 polots) Write a Verilog test bench to test your behavioral ALU model in Part 1f). Assuming that A and B auct-bit. use the following input values: REE R-12 SDR -2 HTR2 Alla period 20 ps here in consecutive les cases. (5 points) Subalit a report (Word or PDF document) that should contain- 2/2 h) i. Problem description il. Your answers to Parts(a) and (b) iii. All the behavioral models dcrived in Part 1, structural model in Part (di, and the test hench in Parl() iv. Thehavioral mcxlel in Pant (and its test hench in Part 1 . The timing diagrams (waves ) taken directly as snapshots rum the simulate Ilave as many ashes as needed in cover all the best caves The assignmcat can be solved individually, or in groups of two studcats. Submit a soft copy of your solution on Blackboard in a zip filc including your Verilog models.

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Answer to You are required to design and implement an ALU with the following ports: • A and B are inputs, and are n-bit signed n…