This issingle-cycle MIPS
I need help addingbgez and lui instructions to the given modules that are providedbelow you only have to add the twoinstructions. I really need the help and it willbe appreciated.
module datapath (inputclk, reset,
input memtoreg, pcsrc,
input alusrc, regdst,
input regwrite, jump,
input [2:0] alucontrol,
output zero,
output [31:0] pc,
input [31:0] instr,
output [31:0] aluout, writedata,
input [31:0] readdata);
wire [4:0]writereg;
wire [31:0] pcnext, pcnextbr, pcplus4, pcbranch;
wire [31:0] signimm, signimmsh;
wire [31:0] srca, srcb;
wire [31:0] result;
// next PC logic
flopr #(32) pcreg(clk, reset, pcnext, pc);
adder pcadd1 (pc, 32’b100, pcplus4);
sl2 immsh(signimm, signimmsh);
adder pcadd2(pcplus4, signimmsh, pcbranch);
mux2 #(32) pcbrmux(pcplus4, pcbranch, pcsrc, pcnextbr);
mux2 #(32) pcmux(pcnextbr, {pcplus4[31:28], instr[25:0],2’b00},jump, pcnext);
// register file logic
regfile rf(clk, regwrite, instr[25:21],
instr[20:16], writereg, result, srca, writedata);
mux2 #(5) wrmux(instr[20:16], instr[15:11],regdst, writereg);
mux2 #(32) resmux(aluout, readdata, memtoreg, result);
signext se(instr[15:0], signimm);
// ALU logic
mux2 #(32) srcbmux(writedata, signimm, alusrc, srcb);
alu alu(srca, srcb, alucontrol, aluout, zero);
endmodule
module controller(input [5:0] op, funct,
input zero,
output memtoreg, memwrite,
output pcsrc, alusrc,
output regdst, regwrite,
output jump,
output [2:0] alucontrol);
wire [1:0] aluop;
wire branch;
maindec md(op, memtoreg, memwrite, branch,
alusrc, regdst, regwrite, jump,
aluop);
aludec ad (funct, aluop, alucontrol);
assign pcsrc = branch & zero;
endmodule
module maindec (input[5:0] op, output memtoreg, memwrite, output branch, alusrc,
output regdst, regwrite, output jump, output [1:0] aluop);
reg [8:0] controls;
assign {regwrite, regdst, alusrc, branch, memwrite, memtoreg, jump,aluop} = controls;
always @ (* )
case(op)
6’b000000 : controls <= 9’b110000010; //Rtyp
6’b100011 : controls <= 9’b101001000; //LW
6’b101011 : controls <= 9’b001010000; //SW
6’b000100 : controls <= 9’b000100001; //BEQ
6’b001000 : controls <= 9’b101000000; //ADDI
6’b000010 : controls <= 9’b000000100; //J
default: controls<= 9’bXXXXXXXXX; //???
endcase
endmodule
module aludec (input[5:0] funct,
input [1:0] aluop,
output reg [2:0] alucontrol);
always @ (*)
case (aluop)
2’b00: alucontrol <= 3’b010; // add
2’b01: alucontrol <= 3’b110; // sub
default: case(funct) // RTYPE
6’b100000: alucontrol <= 3’b010; // ADD
6’b100010: alucontrol <= 3’b110; // SUB
6’b100100: alucontrol <= 3’b000; // AND
6’b100101: alucontrol <= 3’b001; // OR
6’b101010: alucontrol <= 3’b111; // SLT
default: alucontrol <= 3’bxxx; // ???
endcase
endcase
endmodule
module alu (a,b,sel,out, zero);
input [31:0] a,b;
input [2:0] sel;
output reg [31:0] out;
output reg zero;
initial
begin
out = 0;
zero =1’b0;
end
always @ (*)
begin
case(sel)
3’b000:
begin
out=a & b;
if (out == 0)
zero = 1;
else
zero = 0;
end
3’b001:
begin
out= a | b;
if (out == 0)
zero = 1;
else
zero = 0;
end
3’b110:
begin
out=a-b;
if (out == 0)
zero = 1;
else
zero = 0;
end
3’b010:
begin
out=a+b;
if (out == 0)
zero = 1;
else
zero = 0;
end
3’b111:
begin
if ( a < b)
out = 1;
else
out=0;
end
endcase
end
endmodule
Label Instruction MACHINE CODE Comment Instr. ADDR. main: 8 10 14 18 10 20 24 addi $2, $0,5 addi $3,$0,12 addi $7,$3,-9 or $4,$7,$2 and $5,$3,$4 add $5,$5,$4 beg $5,$7,end slt $4,$3,$4 beg $4,$0, around addi $5,$0,0 slt $4,$7,$2 add $7,$4,$5 sub $7,$7,$2 sw $7,68($3) lw $2,80($0) lui $8,0×01 sub $5, $8, $2 bgez $5, end addi $5,$0,1 20020005 2003300C 2067FFF7 OOE22025 00642824 B0A42820 10A7000A 0064202A 10800001 20050000 OOE2202A 00853820 O0E23822 AC670044 8C020050 3C080001 01022822 04A10008 20050001 $2=5 $3= 12 $7= 3 $4=7 $5=4 $5=11 Not taken $450 taken skipped $4=1 $7=12 $7=7 M[80]=7 $2=7 $8 = 0x01 $5 = 6 $5 >= 0 $5 = 1 28 around: 20 30 34 38 30 40 44 48 40 end: sw $5,84($0) ACO50054 M[84]=$5 Show transcribed image text Label Instruction MACHINE CODE Comment Instr. ADDR. main: 8 10 14 18 10 20 24 addi $2, $0,5 addi $3,$0,12 addi $7,$3,-9 or $4,$7,$2 and $5,$3,$4 add $5,$5,$4 beg $5,$7,end slt $4,$3,$4 beg $4,$0, around addi $5,$0,0 slt $4,$7,$2 add $7,$4,$5 sub $7,$7,$2 sw $7,68($3) lw $2,80($0) lui $8,0×01 sub $5, $8, $2 bgez $5, end addi $5,$0,1 20020005 2003300C 2067FFF7 OOE22025 00642824 B0A42820 10A7000A 0064202A 10800001 20050000 OOE2202A 00853820 O0E23822 AC670044 8C020050 3C080001 01022822 04A10008 20050001 $2=5 $3= 12 $7= 3 $4=7 $5=4 $5=11 Not taken $450 taken skipped $4=1 $7=12 $7=7 M[80]=7 $2=7 $8 = 0x01 $5 = 6 $5 >= 0 $5 = 1 28 around: 20 30 34 38 30 40 44 48 40 end: sw $5,84($0) ACO50054 M[84]=$5
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Answer to This is single-cycle MIPS I need help adding bgez and lui instructions to the given modules that are provided below you …