What is the speedup due to pipelining with the followingstages:
FI: Fetch an instruction from memory (4 ns)
DA: Decode the instruction and calculate the effective address ofthe operand (2 ns)
FO: Fetch the operand (4 ns)
EX: Execute the operation (3 ns)
marie
b) (10 pts) What is the speedup if the pipeline above suffered from the following memory access resource conflict? When instructions į and i+2 want to access memory at the same time, i+2 needs to be denied, so it waits for the next cycle; in the next cycle it has a conflict with i+1 so it stalls for another cycle. With one memory, a data and an instruction fetch cannot be initiated in the same clock FIDAFO EX FI DA FO EX stall stall FI DA FO EX The Pipeline is stalled for resource conflict Show transcribed image text b) (10 pts) What is the speedup if the pipeline above suffered from the following memory access resource conflict? When instructions į and i+2 want to access memory at the same time, i+2 needs to be denied, so it waits for the next cycle; in the next cycle it has a conflict with i+1 so it stalls for another cycle. With one memory, a data and an instruction fetch cannot be initiated in the same clock FIDAFO EX FI DA FO EX stall stall FI DA FO EX The Pipeline is stalled for resource conflict
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Answer to What is the speedup due to pipelining with the following stages: FI: Fetch an instruction from memory (4 ns) DA: Decode …