Using VHDL language, Quartus Prime software and Intel DE 10-Lite board, you should design, simulate and implement a “Reaction Timer” circuit. The implementation will use the FPGA to measure the average reaction time of a person to a visual stimulus. A seven segment display will show a series of numbers, and the user is asked to push a button whenever they see a specific number, in the case of this project the number will be “7”. This number sequence is displayed 30 times and the average reaction time to display of 7 is measured. The inputs to the timer are clk, reset, pb1 (start), and pb0 (response input); the outputs are four 7-bit outputs, seg7a3, seg7a2, seg7a1, seg7a0, which will display the average reaction time, and seg7s, displaying the number sequence. Each 7-bit output will drive a seven segment display on the FPGA board. Another output is done, which will output a ‘1’ on LED0 when the average reaction time is available. The outputs of this circuit must be displayed on the 7-segment display units of DE 10-Lite board. Use switche SW0 for reset Procedure The Reaction Timer must be tested in the simulator and verified on the FPGA board as follows 1. Use pbl to begin the test 2. Display a series of 30 numbers on the seven segment display HEX0. When the seven segment display shows 7, the user must push pb0 (Do not start with 7). 3. The time difference between displaying number 7 and pushing pb0 should be measured and recorded 4. The series of numbers, which will be implemented and stored in a memory module and shown on HEX0, must be at least 30 values in length. This dataset should include 5 or more sevens 5. When finished turn on LEDO, by setting done equal to ‘1’, and take the average of the reaction times and show it rounded up to the nearest millisecond on seven segment displays HEX4, HEX3, HEX2, and HEX Hints – Declare libraries -Create a memory module for storing a preset sequence of 30 values that will be used for the reaction timer test – Name of entity must match project name, declare ports of black box within entity, Architecture is where you should declare signals, write processes using sensitivity list, and assign signals to corresponding ports – A clock divider should be used for generating a clock with millisecond count period. – Read the DE 10-Lite board manual to figure out what I/O pins you need to use for this Project Marking GAs will check the results of simulation and functionality of design on the Intel DE 10-Lite boards. Part marks will be given for all aspects 35 percent for working simulation 35 percent for working implementation Show transcribed image text Using VHDL language, Quartus Prime software and Intel DE 10-Lite board, you should design, simulate and implement a “Reaction Timer” circuit. The implementation will use the FPGA to measure the average reaction time of a person to a visual stimulus. A seven segment display will show a series of numbers, and the user is asked to push a button whenever they see a specific number, in the case of this project the number will be “7”. This number sequence is displayed 30 times and the average reaction time to display of 7 is measured. The inputs to the timer are clk, reset, pb1 (start), and pb0 (response input); the outputs are four 7-bit outputs, seg7a3, seg7a2, seg7a1, seg7a0, which will display the average reaction time, and seg7s, displaying the number sequence. Each 7-bit output will drive a seven segment display on the FPGA board. Another output is done, which will output a ‘1’ on LED0 when the average reaction time is available. The outputs of this circuit must be displayed on the 7-segment display units of DE 10-Lite board. Use switche SW0 for reset Procedure The Reaction Timer must be tested in the simulator and verified on the FPGA board as follows 1. Use pbl to begin the test 2. Display a series of 30 numbers on the seven segment display HEX0. When the seven segment display shows 7, the user must push pb0 (Do not start with 7). 3. The time difference between displaying number 7 and pushing pb0 should be measured and recorded 4. The series of numbers, which will be implemented and stored in a memory module and shown on HEX0, must be at least 30 values in length. This dataset should include 5 or more sevens 5. When finished turn on LEDO, by setting done equal to ‘1’, and take the average of the reaction times and show it rounded up to the nearest millisecond on seven segment displays HEX4, HEX3, HEX2, and HEX Hints – Declare libraries -Create a memory module for storing a preset sequence of 30 values that will be used for the reaction timer test – Name of entity must match project name, declare ports of black box within entity, Architecture is where you should declare signals, write processes using sensitivity list, and assign signals to corresponding ports
– A clock divider should be used for generating a clock with millisecond count period. – Read the DE 10-Lite board manual to figure out what I/O pins you need to use for this Project Marking GAs will check the results of simulation and functionality of design on the Intel DE 10-Lite boards. Part marks will be given for all aspects 35 percent for working simulation 35 percent for working implementation
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